1. Field of the Invention
The present invention relates to a semiconductor structure. More particularly, the present invention relates to a chip package structure.
2. Description of Related Art
In a semiconductor industry, integrated circuits (IC) are produced mainly through three stages, namely, IC design, IC process, and IC package.
During the fabricating of the ICs, chips are formed by the steps of wafer manufacturing, IC formation, and wafer sawing. The wafer has an active surface which generally refers to a surface of the wafer on which a plurality of active devices is formed. After the IC within the wafer is finished, a plurality of bonding pads is further formed on the active surface of the wafer, such that the chip finally formed after wafer sawing may be externally electrically connected to a carrier through the bonding pads. The carrier is, for example, a lead frame or a package substrate. The chip may be connected to the carrier by wire bonding process or flip chip bonding process, such that the bonding pads of the chip are electrically connected to contacts of the carrier, thus forming a chip package structure.
FIG. 1A is a cross-sectional view of a conventional chip package structure, and FIG. 1B is a top view of some components of the conventional chip package structure in FIG. 1A. Referring to FIGS. 1A and 1B, for the convenience of illustration, the chip 120 is not shown but is indicated by a dashed line in FIG. 1B. Furthermore, only partial area of a circuit substrate 110 is shown in FIG. 1B.
Referring to FIGS. 1A and 1B together, the conventional chip package structure 100 includes a circuit substrate 110, a chip 120, an adhesive layer 130, a plurality of conductive wires 140, a molding compound 150, and a plurality of solder balls 160. The circuit substrate 110 has a first surface 110a, a second surface 110b, and a slot 112, and the chip 120 is disposed on the first surface 110a and covers at least a portion of the slot 112. Furthermore, the adhesive layer 130 is disposed between the chip 120 and circuit substrate 110, and located at both sides of the slot 112. The chip 120 is fixed to the circuit substrate 110 through the adhesive layer 130. The conductive wires 140 connect the chip 120 and the second surface 110b of the circuit substrate 110 through the slot 112. The molding compound 150 covers the chip 120, the adhesive layer 130, the conductive wires 140, and a portion of the circuit substrate 110, and the molding compound 150 is further filling into the slot 112. The solder balls 160 are disposed on the second surface 110b of the chip 130.
Since the materials of the adhesive layer 130 and molding compound 150 are different in properties, when the conventional chip package structure 100 is subjected to a reliability test, the region A in FIG. 1B may be damaged more possibly than other regions.
FIG. 2 is a top view of some components of another conventional chip package structure. Referring to FIG. 2, for the convenience of illustration, the chip 120, and the chip 120 is not shown but is indicated by a dashed line in FIG. 2. Furthermore, only partial area of the circuit substrate 110 is shown in FIG. 2.
Referring to FIG. 2, in order to reduce the probability that the region A in FIG. 1B may be damaged, in the conventional chip package structure (as shown in FIG. 1A), the adhesive layer 130a exposes the circuit substrate 110 in region A, so that the molding compound 150 may be filled in the region A. However, in order to allow the molding compound 150 to flow into the region A easily, the thickness of the adhesive layer 130a must be increased to extend the distance between the chip 120 and the circuit substrate 110. In other words, the chip package structure has a high cost of material.